1. Field of the Invention
The present invention relates to an image output control apparatus and, more particularly, to an image output control apparatus which superimposes a video image onto such digitally generated types of image as characters and graphics and outputs the superimposed image to a display unit such as a large-screen display.
2. Description of the Prior Art
FIG. 1 is a block diagram of the prior art signal processor disclosed in Japanese Patent Laid-open No. 56-4185, the signal processor being used by display units. In FIG. 1 the signal processor comprises a down counter 1, flip-flop circuit 2, pixel 3, a group of video signal lines 4, a clock pulse input line 5, and a set pulse signal input line 6.
As shown in FIG. 2, many of these parts are arranged in a matrix pattern to constitute one display unit 29. In FIG. 2, reference numeral 8 refers to an A/D converter, and 9 refers to a timing generating circuit. As depicted in FIG. 3, modules 28 are each constituted by a predetermined number of pixels. Data is individually transmitted to each module 28. In FIG. 3, reference numeral 11 designates a group of buffers for waveform shaping purposes, and 12 denotes a group of terminators.
In operation, the effective interval of a video image is converted by the A/D converter 8 into a digital signal containing a predetermined number of bits (six bits per sample hereinafter). In accordance with a timing signal generated by the timing generating circuit 9, the digital signal is sampled for the data corresponding to the number of pixels in the screen (display unit) 29. Particularly on a large-screen display unit, a screen of a desired size may be formed by providing a suitable number of modules 28; sampling is carried out based on the screen size. The sampled data is transmitted over a bus 13 to each buffer memory 10 for temporary storage. The buffer memories 10 convert the data from the bus 13 into data having a lower speed before transmission to each module 28. FIG. 4 is a conceptual view of how the transmission speed is converted by the buffer memories 10. For example, an effective signal of one scanning line (1H) is divided into three parts (H.sub.1, H.sub.2 and H.sub.3 in FIG. 4). The divided signals H.sub.1, H.sub.2 and H.sub.3 are stored temporarily in the buffer memories 10 during periods W.sub.1, W.sub.2 and W.sub.3, respectively. The writing of the three signals to the buffer memories 10 is performed after periods P.sub.1, P.sub.2 and P.sub.3 elapse, respectively, following the completion of writing signals H.sub.1, H.sub.2 and H.sub.3 of the preceding scanning line. That is, the read periods P.sub.1, P.sub.2 and P.sub.3 are fixed relative to the write periods W.sub.1, W.sub.2 and W.sub.3, respectively. Whereas the bus 13 is a high-speed bus through which A/D converted video image signals pass, a second bus 14 is a bus that carries data having the lower data transmission speed. This means that a flat cable may be used as bus 14. For the second bus 14, each buffer memory 10 designates a start address to carry out successive data transmission. The modules 28 receive appropriate data based on these addresses. The data is stored element in a data storage 7 corresponding to each pixel.
FIG. 1 illustrates an example in which the preset part of the down counter 1 is utilized as the data storage element 7. The moment a set signal turns on the flip-flop circuit; 2, six-bit video data is loaded into the down counter 1. Immediately thereafter, the down counter 1 counts clock pulses and outputs a borrow signal at the point in time which corresponds to the loaded data. It is at this point that the flip-flop circuit 2 is turned off and the down counter 1 ends its counting. Depending on the data, the flip-flop circuit 2 is turned on in up to 64 steps to drive the pixel. The above process is repeated, with the data of each pixel updated per field (1/60 sec. for NTSC) in synchronization with the video data. In this manner, an image of up to 64 grades is displayed on the screen.
On the display unit 29 (especially on a large-screen display), a number of display functions are required in addition to the video image display feature. For example, it is sometimes desirable to superimpose characters and graphics onto the video image. The superimposing takes place on the bus 13.
FIG. 5 is a block diagram of the prior art image output control apparatus illustratively disclosed in Japanese Patent laid-open Application No. 60-136828. In FIG. 5 the image control apparatus comprises, a first memory 15 for storing A/D converted video data in units of fields or frames, an I/O device 16 that inputs characters and generates graphic images, a CPU 17 that controls image generation and display, a program memory 18 that stores programs, a disk unit 19 that stores digital data representing characters and graphic images on disk, a disk controller 20 that controls data input and output to and from the disk unit 19, a control bus 21 for transferring data between the CPU 17 and other parts of the system, a DMA bus 22 for transferring the digital data, and a second memory 23 that contains the digital data in units of fields or frames. Data is output from the first memory 15 and the second memory 23 by either of the control circuits shown in FIGS. 7 or 8 and connected thereto. These control circuits are omitted in FIG. 5 so as to simplify the illustration.
In operation, an input video image is converted by the A/D converter 8 into video data which is a digital signal. The video data is placed into the first memory 15. For example, the video data representing the image shown in FIG. 6(a) is stored into the first memory 15. On the other hand, digital data representing the image shown in FIG. 6(b) is generated by the I/O device 16 and the CPU 17. This digital data is written to the disk unit 19. Under control of the CPU 17, the digital data in the disk unit 19 is placed onto the DMA bus 22 via the disk controller 20. The digital data is then stored into the second memory 23 in units of fields or frames. The video data in the first memory 15 and the digital data in the second memory 23 are read therefrom in accordance with a common timing signal, the two kinds of data being output onto the bus 13. This generates composite data representing a composite image as depicted in FIG. 6 (C).
Block 25 represents a converter for converting the data on the bus 13 to television signals and screen symbol 26 denotes a monitor television. The image data synthesized on the bus 13 are displayed at a large-scale display and the displayed contents can be ascertained by the monitor television.
There are two ways to generate composite data. The first way is to have the bus controller 24 tell the first memory 15 and the second memory 23 (using a timing signal) to place their data onto the bus 13 with an appropriate timing which takes the display area of the screen into account. A typical setup implementing this scheme of composite data generation is illustrated in FIG. 8. In FIG. 8, video data generating block 31 comprises the first memory 15, a timing controller 32 and a bus buffer 33. The timing controller 32 receives the timing signal from the bus controller 24 over a timing signal line 13b and tells the first memory 15 to output its data accordingly. The bus buffer 33, using an enable signal (VEN) 34 from the bus controller 24, sends the video data to a data bus 13a of the bus 13. Digital data generating block 35 comprises the second memory 23, a timing controller 36 and a bus buffer 37. The timing controller 36 receives the timing signal from the bus controller 24 and tells the second memory 23 accordingly to output its data. The bus buffer 37, using an enable signal (DEN) 38 from the bus controller 24, transfers the digital data to the data bus 13a of the bus 13. In this manner, the bus controller 24 selectively outputs VEN 34 or DEN 38.
The second way to generate composite data is a scheme in which the bus controller 24 does not output VEN 34 or DEN 38 but determines the priority according to which the video data generating block 31 and the digital data generating block 35 use the data bus 13a. FIG. 7 shows a construction illustrative of this scheme. In FIG. 7, the circuit comprises the video data generating block 31, and the digital data generating block 35 which contains a transparency discriminating circuit 40 and an inverting gate 41. The transparency discriminating circuit 40 checks to see if each pixel of the digital data from the second memory 23 is transparent. The inverting gate 41 inverts the output from the transparency discriminating circuit 40 and supplies the result to the bus buffer 33 of the video data generating block 31. Therefore, when a timing signal is output by the bus controller 24, the second memory 23 is given priority and outputs digital data onto the data bus 13a. If a pixel of the digital data is transparent, the corresponding video data is output from the first memory 15 onto the data bus 13a. In this manner, the video data or digital data is selectively output onto the data bus 13a depending on the digital data content. Composite data is placed onto the data bus 13a in one of the above-described two ways. As a result, a composite image like the one shown in FIG. 6 (C) is displayed on the screen.
Where a large-screen display unit is used, the bus 13 is connected to a plurality of buffer memories 10 according to screen size, as illustrated in FIG. 3. Appropriate data is sent to each module 28, and the target image is displayed on the screen.
A case is assumed in which the images shown in FIG. 9 are displayed. FIG. 9 (A) shows how a video image is superimposed onto a certain portion of a digital image (which is not transparent). This superimposing process can be implemented using the above-described first scheme, i.e., the construction shown in FIG. 8. In this scheme, the bus controller 24 suitably controls VEN 34 and DEN 38. The superimposing process can also be implemented using the second scheme, i.e., the construction depicted in FIG. 7. This is made possible because the video data is output for that portion of the digital data which contains transparent pixels.
FIG. 9 (B) shows a case in which a video image is displayed in a certain area of a digital image, followed by another display of the initial digital image. This superimposing process is implemented using the first scheme. This is made possible because the bus controller 24 suitably controls VEN 34 and DEN 38. However, the second scheme cannot be used because it is a scheme that superimposes a digital image onto a video image. Under this scheme, it is impossible not to display that portion of the digital data which contains untransparent pixels. If the second scheme must be used, a separate frame memory most be provided so that the data representing the composite image may be stored therein. Upon completion of the display, the initial digital data needs to be written again to the frame memory. This means that while data is being written to the frame memory upon display switch, there occurs an awkward transition between display modes on the display screen.
FIG. 9 (C) shows a case in which a character digital image is superimposed onto a video image. This superimposing process is implemented using the second scheme but not the first scheme. The reason for this is that under the first scheme, the bus controller 24 would have to control VEN 34 and DEN 38 for each pixel of the font of characters to be displayed; the bus controller 24 does not have provisions for fonts and is incapable of providing control of the above kind.
Given the above-described structure, the prior art image output control apparatus has a number of disadvantages, one of which is its inability to implement the superimposing of a plurality of images into a composite image. With its construction in FIG. 8, the apparatus is incapable of superimposing characters onto a video image; with its construction in FIG. 7, the apparatus cannot superimpose a desired video image onto a digital image.
Another disadvantage of the prior art apparatus is that where a large-screen display is used, the apparatus often has difficulty in implementing a plurality of screens as shown in FIG. 10.
FIGS. 10 (A)-10 (D) illustrate examples in which one or a plurality of screens 29a-29c are displayed on the single display unit 29, each screen containing a composite image made of a video image 291 and a digital image 292.